Essential Knowledge for Transistor-Level LSI Circuit Design by Toru Nakura

Author:Toru Nakura
Language: eng
Format: epub
Publisher: Springer Singapore, Singapore

As an extreme example, when Z s  = Z 0 (matched termination) and (open termination), the situation is in between Fig. 5.7b, c, and I 1f  = V 0∕(2Z 0), V 1f  = V 0∕2, , , , , I 2f  = 0, and V 2f  = 0. That is, the voltage at the receiving end is zero until the signal arrives, and at time T p becomes V 0∕2, but the arrival and reflection occur simultaneously and the voltage becomes V 0 (V 1f  = V 1b  = V 0∕2, V 1f + V 1b  = V 0). The current traveling right is zero until the signal arrives, and the moment the signal arrives, it becomes I 1f , but the arrival and reflection occur simultaneously and the current becomes zero (I 1f  = I 1b , I 1f − I 1b  = 0). The voltage at the transmitting end is V 0∕2 until the reflected wave arrives and becomes V 0 when the reflected wave does arrive. The current traveling right at the transmitting end is I 1f until the reflected wave arrives and zero after the reflected wave does arrive. Another reflection does not occur ().

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